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DR80390
High Performance 8-bit Microcontroller ver 3.10
OVERVIEW
DR80390 is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about low power consumption. Additionally an advanced power management unit makes DR80390 core perfect for portable equipment where low power consumption is mandatory. DR80390 soft core is 100% binarycompatible with the industry standard 80C390 8-bit microcontroller. There are two configurations of DR80390: Harward where external data and program buses are separated, and von Neumann with common program and external data bus. DR80390 has RISC architecture 6.7 times faster compared to standard architecture and executes 65-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty. DR80390 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.
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CPU FEATURES
100% software compatible with industry standard 80390
LARGE mode - 8051 instruction set FLAT mode - 80390 instruction set
RISC architecture enables to execute instructions 6.7 times faster compared to standard 8051 12 times faster multiplication 9.6 times faster division Up to 256 bytes of internal (on-chip) Data Memory Up to 16M bytes of contiguous Program Memory Up to 16M bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed De-multiplexed Address/Data bus to allow easy connection to memory Interface for additional Special Function Registers
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Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states Scan test ready 1.3 GHz virtual clock frequency in a 0.35u technological process
Read/write of single line and 8-bit group
Two 16-bit timer/counters
Timers clocked by internal source Auto reload 8-bit timers Externally gated event counters
Full-duplex serial port
PERIPHERALS
DoCDTM debug unit
Processor execution control Run Halt Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated at a certain Program address (PC) Address by any write into memory Address by any read from memory Address by write into memory a required data Address by read from memory a required data Three wire communication interface
Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DR80390 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.
* Memory style * Program Memory type * Program Memory waitstates - Harward - von Neumann - synchronous - asynchronous - used (0-7) - unused - used - unused - synchronous - asynchronous - used (0-7) - unused subroutines location
* Program Memory writes * Internal Data Memory type * External Data Memory wait-states
* Interrupts * Power Management Mode * Stop mode * DoCD debug unit
Power Management Unit
Power management mode Switchback feature Stop mode
- used - unused - used - unused - used - unused
Interrupt Controller
2 priority levels 2 external interrupt sources 3 interrupt sources from peripherals
Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.
Four 8-bit I/O Ports
Bit addressable data direction for each line All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance

Single Design to Unlimited Designs
SYMBOL
clk reset ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(23:0) prgrd prgwr xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr docddatao docdclk stop pmm port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
sfrdatai(7:0)
prgdatai(7:0)

xramdatai(7:0)
Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support
int0 int1 docddatai
LICENSING
Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for
VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) t0 gate0 t1 gate1 rxd0i
rxd0o txd0
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source Netlist
Upgrade from
HDL Source to Netlist All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl
Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
clk reset prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(23:0) prgrd prgwr xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe docddatai docddatao docdclk
Opcode Decoder ALU
ramdatao[7:0] ramaddr[7:0] ramoe ramwe sfrdatao[7:0] sfraddr[7:0]
output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output
Data bus for Internal Data Memory Internal Data Memory address bus Internal Data Memory output enable Internal Data Memory write enable Data bus for user SFRs User SFRs address bus User SFRs output enable User SFRs write enable Program Memory address bus Output data bus for Program Memory PRGDATA tri-state buffers control line Program Memory read Program Memory write Data bus for External Data Memory XDATA tri-state buffers control line External Data Memory address bus External Data Memory read External Data Memory write DoCDTM data output DoCDTM clock line Power management mode indicator Stop mode indicator Port 0 output Port 1 output Port 2 output Port 3 output Serial receiver output 0 Serial transmitter line 0 Serial receiver output 1 Serial transmitter line 1
Program Memory Interface
sfroe
Control Unit
sfrwe prgaddr[23:0] prgdatao[7:0]
External Memory Interface
Interrupt Controller
int0 int1
prgdataz prgrd prgwr xramdatao[7:0]
Internal Data Memory Interface I/O Ports User SFR Interface
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
xramdataz xramaddr[23:0] xramrd xramwr docddatao docdclk pmm stop port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] rxd0o txd0 rxd1o txd1
DoCDTM Debug Unit
Power Management Unit
stop pmm
rxd0o rxd0i txd0
UART 0
Timers 0 & 1
t0 gate0 t1 gate1
PINS DESCRIPTION
PIN
clk reset ramdatai[7:0] sfrdatai[7:0] prgdatai[7:0] xramdatai[7:0] int0 int1 docddatai port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] t0 gate0 t1 gate1 rxd0i
TYPE
input input input input input input input input input input input input input input input input input input
DESCRIPTION
Global clock Global synchronous reset Data bus from Internal Data Memory Data bus from user SFRs Input data bus from Program Memory Data bus from External Data Memory External interrupt 0 line External interrupt 1 line DoCDTM data input Port 0 input Port 1 input Port 2 input Port 3 input Timer 0 clock line Timer 0 clock line gate control Timer 1 clock line Timer 1 clock line gate control Serial receiver input 0
UNITS SUMMARY
ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface - Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
program into RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCDTM module. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. External Memory Interface - Contains memory access related registers such as Data Pointer High (DPH0), Data Pointer Low (DPL0), Data Page Pointer (DPP0), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. Allows applications software to access up to 16 MB of external data memory. The DPP0 register is used for segments swapping. STRETCH register allows flexible timing management while accessing different speed system devices by programming XRAMWR and XRAMRD pulse width between 1 - 8 clock periods. Internal Data Memory Interface - Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8-bit Stack Pointer (SP) register and related logic. User SFRs Interface - Special Function Registers interface controls access to the special registers. It contains standard and used defined registers and related logic. User defined external devices can be quickly accessed (read, written, modified) using all direct addressing mode instructions. Interrupt Controller - Interrupt control module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers. I/O Ports - Block contains 8051's general purpose I/O ports. Each of port's pin can be read/write as a single bit or as an 8-bit bus called P0, P1, P2, P3. Power Management Unit - Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications.
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DoCDTM Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other onchip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. Timers - System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs. UART0 - Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1.
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PERFORMANCE
The following tables give a survey about the Core area and performance in ASICs Devices (CPU features and peripherals have been included):
Device 0.25u typical 0.25u typical Optimization area speed Fmax 100 MHz 250 MHz
45000 40000 35000 30000 25000 20000 15000 10000 5000 0 268 1550
40125
Core performance in ASIC devices
For a user the most important is application speed improvement. The most commonly used arithmetic functions and their improvements are shown in table below. An improvement was computed as {80C51 clock periods} divided by {DR80390 clock periods} required to execute an identical function. More details are available in core documentation.
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 7,20 6,00 6,00 7,20 7,20 6,00 6,00 7,20 10,67 9,60 7,20 7,64 9,75 7,20 7,43 9,04 7,58
80C51 (12MHz)
80C310 (33MHz)
DR80390 (250MHz)
Area utilized by the each unit of DR80390 core in vendor specific technologies is summarized in table below.
Component CPU* Interrupt Controller Power Management Unit I/O ports Timers UART0 Total area Area
[Gates] [FFs]
5500 450 50 400 550 650 7600
250 40 5 35 50 60 430
*CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following table gives a survey about the DR80390 performance in terms of Dhrystone/sec and VAX MIPS rating.
Device 80C51 80C310 DR80390 Target 0.25u Clock frequency 12 MHz 33 MHz 250 MHz Dhry/sec (VAX MIPS) 268 (0.153) 1550 (0.882) 40125 (22.837)
Core performance in terms of Dhrystones
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
The main features of each DR80390 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications.
Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States
Architecture speed grade
Compare/Capture
Interrupt sources
Stack space size
Timer/Counters
Interrupt levels
Master I2C Bus Controller Slave I2C Bus Controller
Design
DR80390CPU 6.7 16M 256 256 16M DR80390 6.7 16M 256 256 16M DR80390XP 6.7 16M 256 256 16M
2 5 15
2 2 2
1 1 2
2 3
1 2
4 4
-
-
-
-
-
-
DR80390 family of High Performance Microcontroller Cores
The main features of each DR8051 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications.
Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States
Architecture speed grade
Compare/Capture
Interrupt sources
Stack space size
Timer/Counters
Interrupt levels
Master I C Bus Controller Slave I2C Bus Controller
Design
DR8051CPU DR8051 DR8051XP
6.7 64k 256 256 16M 6.7 64k 256 256 16M 6.7 64k 256 256 16M
2 5 15
2 2 2
1 1 2
2 3
1 2
4 4
-
-
-
-
-
-
DR8051 family of High Performance Microcontroller Cores
All trademarks mentioned in this document are trademarks of their respective owners.
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Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.
Fixed Point Coprocessor Floating Point Coprocessor -
Data Pointers
Watchdog
I\O Ports
UART
2
SPI
Fixed Point Coprocessor Floating Point Coprocessor -
Data Pointers
Watchdog
I\O Ports
UART
SPI
CONTACTS
For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinffo@dcd..pll n o@dc d p tel. fax : +48 32 282 82 66 : +48 32 282 74 37
Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245, USA e-mail: iinffoUS@dcd..pll n oUS@dcd p tel. fax : +1 210 422 8268 : +1 210 679 7511
Distributors: Please check htttp::///www..dcd..pll//aparrttn..php h p www dcd p apa n php
All trademarks mentioned in this document are trademarks of their respective owners.
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